High-Throughput Memory-Optimized Digital Circuits to Calculate 2D Convolutional Filters

This paper proposes novel digital circuits for computing two-dimensional convolutional filters in image processing applications. These circuits are designed for different data rates and process multiple samples arriving in parallel, making them suitable for high-throughput real-time applications. The key advantage of the proposed circuits is that they optimize memory usage so that it does not increase with the parallelization. This makes them more efficient than multiple serial architectures working in parallel, which are commonly used in the literature. To design the proposed circuits, we analyze the mathematical operations involved in the calculations and optimize the trade-off between throughput and area usage. To evaluate the performance of the proposed designs, the circuits are analyzed with respect to throughput, power consumption, and area utilization. Given the achieved throughput, these architectures substantially lower hardware resource usage and power consumption on field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) when compared with recent approaches reported in the literature.