Hardware Acceleration with Tunable SRAM/IMC Voltages

Deep Neural Networks (DNNs) are the fundamental component in most artificial intelligence applications. With the increasing number of applications based on artificial intelligence, the performance and energy efficiency of architectures running these algorithms have become crucial, especially for battery-powered platforms. In this work, I propose an energy optimizing memory design framework with a special SRAM/in-memory-computing structure. It also utilizes datapath optimization techniques like quantization and pruning with a fine-level assignment. Compared to other hardware accelerator studies for DNN processing, in this work, I will show that this special memory design, together with the architectural datapath optimization techniques, will have a much better capability of finding the Pareto optimal point in the energy-accuracy trade-off and increase the profitability of the final design.